Refer to the "CSEL Encodings for hps_clk_f = 0" table in the If FPGA configuration fails, HPS shared and SDRAM I/Os are placed in an input tristate mode.
The Arria 10 So C device supports both a default and a faster boot clock mode.
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does not guarantee automatic lane polarity inversion with the Gen1x1 configuration, Configuration via Protocol (Cv P), or Autonomous Hard IP mode.
The link may not train successfully, or it may train to a smaller width than expected. For all other configurations, refer to the following workaround.